1. Field of the Invention
The present invention relates to the field of computer memory hardware. More particularly, the present invention relates to an improved memory circuit board apparatus designed to perform with computer systems notwithstanding the lack of an industry standard memory devices organization and providing for the use of certain types of memory devices having non-standard depths.
2. Brief Description of the Prior Art
A computer system typically requires a certain minimum amount of memory in order to operate at an acceptable level of processing speed. If more memory is added to the computer system, there will be a higher level of computational speed.
One type of memory module is the Single In Line Memory Module ("SIMM") wherein a number of memory devices (chips) are mounted on a small circuit board having an edge connector with a number of pins. These memory devices can be either dynamic random access memory devices ("DRAM") or static random access memory devices ("SRAM"). The number of addressable locations within the memory device is referred to as the depth of the device. Size or depth of memory devices is typically referred to in units of "K" and "M", with 1K being 1024 units and 1M being 1024K units.
SIMMs can be readily plugged into or removed from a system board designed to accept such SIMMs. The SIMMs receive all necessary power, ground, and logic signals from the system board.
In order to provide compatibility between computer system and memory modules from the various manufacturers, the JEDEC council of the Electronic Industries Association provides a number of industry standards. By designing and producing system boards and memory modules according to these standards, compatibility between the different system boards and memory modules is ensured. More specifically, JEDEC Standard No. 21-C covers memory modules and cards, including the 72-pin DRAM Module Family. Under this standard, the following memory configurations for 72-pin DRAM memory modules are specified:
TABLE 1 ______________________________________ Configuration Depth of Memory Device Banks ______________________________________ 256K .times. 36 256K 1 512K .times. 36 256K 2 1M .times. 36 1M 1 2M .times. 36 1M 2 4M .times. 36 4M 1 8M .times. 36 4M 2 ______________________________________
Note that the depths of the memory devices in Table 1 are 256K, 1M, or 4M. Since this standard supports either one or two banks of memory, certain new memory DRAMs with single Row Address Strobe ("/RAS") control signals cannot be used in the above configurations. For example, DRAMs such as the 512K.times.8 DRAM with single RAS control signal, the 2M.times.8 DRAM with single RAS control signal, and the 8M.times.8 DRAM with single RAS control signal are available (or will soon be available) but cannot be used in the above JEDEC specified configurations. However, they can be used in the following configurations:
TABLE 2 ______________________________________ Configuration Depth of Memory Device Banks ______________________________________ 512K .times. 32/36 512K 1 2M .times. 32/36 2M 1 8M .times. 32/36 8M 1 ______________________________________
Note that the depth of the memory devices in Table 2 includes 512K, 2M, and 8M. However, the above memory module configurations are not compatible with computer systems conforming to JEDEC standards because these configurations are not provided under the JEDEC standard.
More specifically, because computer systems conforming to the JEDEC standard do not accommodate 512K, 2M, or 8M memory devices on memory modules, they do not provide the needed address signals for these configurations. For example, under the JEDEC standard, a 2M.times.36 configuration has to use two banks of 1M deep memory devices (see Table 1), rather than one bank of 2M deep memory devices (see Table 2). A memory module using one bank of 2M deep memory devices will not function properly because the computer system only provides ten address signals to address 1M deep memory devices rather than the needed eleven address signals to address 2M deep memory devices. Specifically, the address signals A9 for the 512K deep DRAM, A10 for the 2M deep DRAM, and A11 for the 8M deep DRAMs are not provided. Thus, these memory devices cannot be used unless some specific logic is provided.
As the supply and demand of memory devices fluctuate and the memory devices of Table 2 become widely available and provide better price/density ratio, there is a strong incentive to use these non-standard configurations and memory devices. For example, 1M.times.4 DRAMs are becoming less available while 2M.times.8 DRAMs are becoming more readily available and their prices are dropping.
In addition to the cost consideration, using the nonstandard memory devices also reduces power consumption. By using only 1 bank of memory devices instead of two banks of memory devices as required under the JEDEC standard, less power is needed. Also, capacitive loading is drastically reduced, due to the use of fewer devices, thus providing better capability to increase the number of SIMMs installable in the computer system.
There are several problems presented in using memory devices not provided for under the JEDEC standard. Before discussing these problem, memory module configuration according to the JEDEC standard is explained in detail.
Referring now to FIG. 1 of the drawing, an electrical schematic depiction of a two bank, two megabit ("Mb") deep.times.36 memory module configuration according to the JEDEC standard specification is illustrated. This memory module is comprised of a circuit board, as suggested by the dashed lines 9, adapted to carry two banks 10 and 12 of memory blocks, and includes means for conducting a set of input signals 30-46, a set of output signals, and an output bus 47. Each bank in this configuration includes four 1Mb .times.9 memory blocks 14, 16, 18, and 20 in bank 10, and memory blocks 22, 24, 26, and 28 in bank 12. Each 1 Mb.times.9 memory block can be comprised of two 1 Mb.times.4 memory devices plus a 1 Mb.times.1 memory device, nine 1 Mb.times.1 memory devices, or other combinations of memory devices. Each memory device is a single IC chip contained within a standard device package. Under the JEDEC standard for 72 pin SIMMs, only 1M deep memory devices can be used instead of 2M deep memory devices.
There are a number of input signals to be applied to each of the memory devices. These signals include four Column Address Strobe ("CAS") signals, "/CAS0" input at 36, "/CAS1" input at 34, "/CAS2" input at 32, and "/CAS3" input at 30, four Row Address Strobe ("RAS") signals, "/RAS0" input at 38, "/RAS1" input at 40, "/RAS2" input at 42, and "/RAS3" input at 44, a Write Enable ("/WE") signal input at 45, and ten address signals (A0-A9) input at 46. There are also power input signals, ground signals, and an Output Enable ("/OE") signal which in the interest of simplicity are not shown. The /OE signal is typically grounded in this configuration.
Note that the /RAS, /CAS, /OE, and/WE signals are active low signals, meaning "ON" or active when there is a low voltage level on the line and "OFF" when there is a high voltage level on the line. Active low signals such as the CAS signals are commonly expressed as "/CAS", or with a horizontal bar over it. Further note that it is understood that the various signals are propagated on the circuit board to various components or pins via electrical traces or lines.
The CAS and RAS signals in conjunction allow addressing of each of the memory blocks. By activating the corresponding RAS and CAS signals each memory block can be individually selected. Once the memory block is selected, the specific location within the memory block is accessed via the address signals, A0-A9. With these ten address signals, 1M deep memory locations can be accessed. Depending on a high or low /WE signal, a read or write operation can be made to the addressed memory location.
In a read operation, the corresponding data from the addressed location is sent out to the data bus 47. For example, memory block 20 or 28 sends out 9 bits of data via a sub-bus 48 to the data bus 47; and memory block 18 or 26 sends out 9 bits of data via another sub-bus 50 to the data bus 47. Memory block 16 or 24 and memory block 14 or 22 send out another 18 bits of data via sub-buses 52 and 54 for a total of 36 bits to the data bus 47.
Note that there are 9 bits of data obtained from each memory block in this illustration. The 9 bits of data is typically 8 bits of information data and 1 parity bit for error checking. With a set of four blocks of memory devices, there are a total of thirty-six bits. While under the JEDEC standard 36 bits of data are specified, in other configurations where there are no parity bits, each memory block outputs 8 bits of data for a total of thirty-two bits of data. In this case, a data bus width of thirty-two bits is sufficient. The present invention will work with both cases.
In order to use one bank of 2M deep memory devices, instead of two banks of 1M deep memory devices, there are several problems that need to be resolved. First of all, because the computer system recognizes the memory module as a two bank, 1M deep memory device module instead of a one bank, 2M deep memory device module, it will provide the same set of signals as illustrated in FIG. 1. However, with ten address signals, only 1M depth can be addressed. The second 1M depth cannot be accessed without additional circuit logic to provide an additional address signal. Furthermore, with only four memory blocks in an one bank system, instead of eight memory blocks in the two bank system, only two RAS signals are needed rather than the four RAS signals provided by the computer system. Additional logic is also needed to translate the four RAS signals into two RAS signals for the memory blocks.